System and method for rate agile adaptive clocking in a packet-based network

ABSTRACT

A system for transmitting a clock signal through a packet-based network is disclosed. The system comprises a first node configured to measure a clock frequency of the clock signal and calculate an accuracy indicator of the measured clock frequency; a second node configured to receive the clock frequency measurement and the accuracy indicator of the clock frequency measurement, and synthesize the clock signal therefrom; and a packet-based network for transmitting the measured clock frequency and accuracy indicator from the first node to the second node. A method of deriving a clock frequency by identifying packets with the shortest total transmission time is also disclosed.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims benefit to U.S. provisional patent applicationNo. 60/416,925 filed Oct. 9, 2002, which is hereby incorporated byreference.

INTRODUCTION

Traditionally, Time Division Multiplex (TDM) networks have been one typeof network used to send serial data between two or more remotelocations. In a TDM network, multiple serial data streams are combinedinto a single aggregate signal and transported over a synchronousnetwork. Each data stream is separated into many segments, and eachsegment is assigned a different time slot of the aggregate in a timescheme. TDM networks repeatedly transmit a fixed sequence of time slotsover the aggregate transmission channel. At the receiving end of thenetwork, the data streams are reassembled according to the timing schemeof the network. Synchronization of the timing scheme is a verysignificant factor in accurate data transport.

TDM network components, herein referred to as TDM nodes, are generallysynchronized to a high accuracy clock reference or network clock. If thenodal clocks are not actually synchronized to the same network clock, orreferenced back to the same clock source, they may each be synchronizedto independent clock sources that are of sufficient accuracy so that theTDM nodal clocks may be considered synchronized. Nodal clocks using thissynchronization technique are said to be “pleisiochronous”. Nodal clocksare then available in each node for generating port clocks forindividual user circuits.

Data Terminal Equipment (DTE) comprises remote circuits connected to anode of a communications network. DTE's joined by a TDM network may eachhave a user clock which typically operates synchronously to the nodalclock. This means that the clock used by the connecting equipment tosend and receive data to and from the TDM network is based on a clockgenerated from the internal node clock. In effect, trickle downsynchronization is achieved from the network clock to the nodal clock tothe user clock. Since each node is generating clocks that are derivedfrom the same reference clock or source, the rate at which data entersand exits the TDM network is the same at each end, and no errors occurfrom buffer over or underflow.

There are, however, DTEs that cannot accept a user clock synchronized bythe nodal clocks. If the transmitting DTE's user clock is notsynchronized to the nodal clock and/or the system clock, the receivingDTE's user clock needs to be synchronized to the transmitting DTE's userclock in order to prevent buffer over or underflow that occurs when thedata rate entering and exiting the buffers is not the same.

Instead of being synchronized to a nodal clock, the receiving DTE's userclock must be synchronized to the transmitting DTE's user clock. Theseuser clocks may be synchronized to a clock frequency that may beasynchronous to the network clock and/or nodal clocks. This requiresspecial support on the part of the TDM nodes to transport the data tosynchronize the user clocks. That is, data based on the transmittingDTE's user clock must be passed through the network. Support forsynchronization between the transmitting clock and the receiving clockis referred to as “adaptive clocking”, wherein the receiving DTE isconfigured to recover the transmitting DTE's user clock in order toretrieve the serial data out of the network with a low error rate. Inthis case, the TDM network is configured to transport the dataasynchronously to the rest of its network-synchronized data and oftenrequires additional bandwidth to do so.

A Phase Locked Loop (PLL) typically performs this clock recovery. Sincedata in a TDM network is transported in fixed time slots according tothe network and nodal clocks, the receiving TDM node receives a streamof data at a constant rate. The asynchronous behavior between thenetwork and user clocks is regular and uniform, making the task ofrecovering the user clock easy to support. Also, due to the generallyregular and consistent arrival rate of data from the TDM network, thereis a low error-rate given that there are few buffer overflow orunderflow events. A constant stream of data is provided to the PLLcircuit for retrieving the user clock at the receiving DTE.

A need has been demonstrated to transmit and receive serial data acrossa packet-based network. Clock recovery for adaptive clocking becomesmuch more difficult when the arrival rate of data at the receiving endis not constant, such as in an Internet Protocol (IP) network. An IPnetwork is a packet-based network where data transmission does notdepend on the synchronization of clocks. There are significantcharacteristics of IP networks that make clock recovery very difficult.

One obstacle to clock recovery in an IP network is that data passthrough an IP network in a very different manner than in a TDM network.Unlike TDM networks, where there is bit- or byte-interleaving of data inregular time slots, IP networks transfer packets of data. A packetgroups transmission data together forming a discrete package, whichusually ranges between 32 bytes and 1500 bytes or more. At a receivingnode of an IP network, data arrive in “bursts” according to packet size.For instance, a receiving end may receive a burst of 1200 bytes of data,followed by a delay, and then another burst of 1500 bytes of data. Theirregular rate at which data are received makes it very difficult for aclock recovery device to derive and lock-on to a transmitting DTE userclock signal.

The irregular rate at which packets are received at a remote node alsocomplicates clock recovery in an IP network. Packet arrival times at areceiving end are often quite variable. Congestion on the network andpacket prioritization can cause some packets to be either delayed ordropped altogether from the network. As mentioned before, packets can bevariable in size. For example, Ethernet imposes a maximum packet size of1500 bytes. A maximum packet size of 1000 bytes is common on X.25networks. These packets sizes are not absolute, and packet sizes canusually range from 32 bytes to 1500 bytes or more. With such a largeswing between minimum and maximum packet sizes, packet jitter increasesacross the network. The design of IP networks permits packets to takevarying routes between the nodes on the network, also increasing delayjitter. These factors greatly complicate the task of clock recovery by areceiving DTE.

To implement adaptive clocking on an IP network, information is gatheredfrom the packets arriving from the IP network, and used to recreate aclock that is nominally the same as the one at the transmitting node.

The present invention provides an improved system and method foradaptive clocking in an IP network that allows the receiving node tosynthesize a transmitting clock of any frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, where like reference numbers refer to like elementsthroughout the several views:

FIG. 1 is a block diagram of a system on an IP network that supportsadaptive clocking in accordance with the present invention;

FIG. 2 is a flow chart showing the process for capturing thetransmitting DTE's clock frequency;

FIG. 3 is a graph indicating the measurement accuracy of thetransmitting DTE's captured clock frequency as a function of time;

FIG. 4 is a flow chart showing the process for recovering the clocksignal at a receiving node;

FIG. 5 is a graph showing an example of variations in packet delay in anP network;

FIG. 6 is a graph showing variations in a transmitting clock and packetdelay variation in an IP network;

FIG. 7 is a graph showing clock variation determined through luckypacket identification;

FIG. 8 is a graph showing clock variation determined through continuouslucky packet identification;

FIG. 9 is a graph illustrating three stages in the multistage adaptiveclocking process of the present invention.

FIG. 10 is a graph illustrating Maintain and Derived stages in themultistage adaptive clocking process of the present invention.

DETAILED DESCRIPTION

Known methods of performing adaptive clocking in an IP network aretypically limited to situations in which a receiving clock is first setto a known nominal rate that is near the frequency of the transmittingclock. Minor adjustments are made to the receiving clock according toinformation received over the network about the transmitting clock inorder to synchronize the receiving clock to the transmitting clock. Thetransmitting clock information typically comprises delta typeinformation, such as the difference between the transmitting clockfrequency and the frequency of a highly reliable master clock. There aremany limitations to these known methods. For example, these methods donot work in situations in which the nominal frequency of thetransmitting clock is unknown. It would be beneficial to be able toperform adaptive clocking for any clock rate. Integration of the packetarrival times over very long periods of time would allow a clockrecovery circuit to discern the average data rate of a stream of datapackets and synthesize a clock that approximates the user's input clock.However, gathering data arrival information to calculate and synthesizean appropriate user clock can take an excessive amount of time.

The present invention provides a method and system of quicklysynthesizing a transmitting DTE's clock at a remote node to allow foradaptive clocking in a packet-based network. The inventive method doesnot require prior knowledge of any nominal speed, as absolute, ratherthan differential, measurements are used to send the transmittingclock's speed over the network. The system of the present inventionsynthesizes the transmitting clock by incrementally converging on thedesired frequency.

Referring now to FIG. 1, communication system 100 comprises atransmitting node 102, a receiving node 104, and a packet-based network106 for communication there between. Nodes 102 and 104 may have nodalclocks 109, 111 respectively. Nodal clocks 109 and 111 may besynchronized to master clock 115.

Transmitting node 102 provides an ingress point for serial data passedthrough network 106. Node 102 is configured to receive a clock signal112 and generate a plurality of clock frequency measurements thereon.Transmitting node 102 comprises measurement hardware for generatingthese frequency measurements with increasing accuracy. Node 102transmits the clock frequency measurements across network 106 inaccordance with network protocols.

Node 102 comprises at least one port 108 through which a transmittingDTE 110 is operatively connected. Transmitting DTE 110 supplies theserial data that is supported by clock signal 112 for transmissionacross network 106. Node 102 packages the serial data according to theprotocols of packet-based network 106 for transmission. The serial datamay be bit- or byte-synchronous data.

While the present embodiment shows the transmitting DTE 110 directlyconnected to transmitting node 102 via port 108, it should beappreciated that in alternative embodiments an intervening element mayoperatively bridge the connection between the transmitting DTE and thetransmitting node. The intervening element may embody, for example, anencryption element for encrypting the serial data from the transmittingDTE for secure transmission across network 106.

It should further be appreciated that in alternative embodiments, theintervening element may be configured to receive a second clock signal,such as a black station clock signal.

Referring now to the present embodiment, receiving node 104 performsclock recovery at an egress point on network 106. Receiving node 104 isconfigured to receive the clock frequency measurements from network 106and synthesize clock signal 112 therefrom.

Node 104 comprises at least one port 114 through which a receiving DTE116 is operatively connected to receive clock signal 112. Node 104includes signal synthesizing hardware. In the present embodiment, thisincludes a signal generator such as a Direct Digital Synthesizer (DDS)for synthesizing clock signal 112 using the frequency measurements fromtransmitting node 102. Receiving node 104 transmits synthesized clocksignal 112 to receiving DTE 116. DTE 116 retrieves the serial data fromnode 104 according to the synchronization scheme of clock signal 112.

A hybrid approach to adaptive clocking is set forth herein comprising afirst phase (Phase 1) and a second phase (Phase 2). Each phase isdistributed across both nodes 102, 104. Phase 1 of the hybrid approachcaptures and recovers the signal of user clock 112. Phase 1 includes thesteps of measuring, with increasing accuracy, the signal frequency ofuser clock 112 at transmitting node 102, transmitting the frequencymeasurements to receiving node 104, and recovering the signal of userclock 112 from the frequency measurements at receiving node 104. Phase 2of the hybrid approach maintains the appropriate frequency of therecovered clock signal at receiving node 104. Phase 2 includes the stepsof monitoring, at transmitting node 102, the signal frequency of userclock 112 for transitions, and adjusting the recovered signal withrespect thereto at receiving node 104.

FIG. 2 shows control flow of a measuring process 200 performed attransmitting node 102. The demarcation between Phase 1 steps and Phase 2steps is shown.

Phase 1 begins at control block 202 by triggering a full frequencymeasurement time. This time is preferably a 128-second timer. It opens a128 second window for capturing the frequency of user clock 112.

The full frequency measurement period of 128 seconds will provide a fullfrequency measurement having accuracy within 1/128 Hz of the true signalfrequency. It should be appreciated that alternative embodiments mayincrease or decrease the temporal period driven by the requirements ofthe system or synthesizing granularity of the DDS at the receiving node.

At control block 204, a phase 1 indicator is set that will betransmitted to receiving node 104 to trigger phase 1 therein. At controlblocks 206-218, the frequency measurement hardware of transmitting node102 captures the clock signal frequency of user clock 112 through aplurality of frequency measurements.

The frequency counter takes a full accurate measurement of its inputclock once every full frequency measurement period, or 128 seconds.However, every half second (or other predetermined time period), anincremental measurement value is saved to a register, along with itsrelative accuracy. This allows the frequency counter to reveal thefrequency of what it is measuring with steadily increasing accuracyuntil the full frequency measurement period is complete. Therefore,although the initial measurements from the counter are relativelyinaccurate, they will quickly get progressively better as incrementalmeasurements are made.

A full frequency measurement comprises a plurality of incrementalfrequency measurements taken at periodic intervals within the 128-secondperiod. Each incremental frequency measurement is transmitted toreceiving node 104 as will be described herein, each subsequentincremental measurement having greater accuracy with respect to theactual frequency of clock 112. The frequency measurement taken at theend of the 128-second period is the full accuracy frequency measurementhaving accuracy within ± 1/128 Hz, assuming the first incrementalfrequency measurement is within ±1 Hz.

In one embodiment, the measurement hardware comprises a counter fortallying clock edges that embody the frequency measurements. At controlblock 206, the measurement hardware is started to produce a frequencymeasurement of clock 112. The frequency measurement is retrieved fromthe counter (or other measurement hardware) at control block 208. Thefrequency measurement is tagged with the phase 1 indicator, and istransmitted to receiving node 104 at control block 210 in accordancewith the protocols of packet-based network 106.

At control block 212, the current frequency measurement is normalizedwith respect to the first frequency measurement to obtain an accuracyindicator. The accuracy indicator suggests a relative accuracymeasurement of the most recent frequency measurement. The accuracyindicator is sent to the receiving node with the frequency measurement.The frequency measurement and the accuracy indicator are used togetherby the receiving node to synthesize the transmitting clock at thereceiving node. In one embodiment, the frequency measurement is thenumber of edges counted, and the accuracy indicator is the time period.The frequency measurement is multiplied by the accuracy indicator tosynthesize the transmitting clock at the receiving node.

At decision block 214, the accuracy indicator is compared to a ±1/X₁ Hzthreshold, wherein X₁ is the time interval between each partial accuracyfrequency measurement taken. As will be apparent to those skilled in theart, other values could be used as the threshold. In the example givenabove, X₁ is one-half of a second. If the accuracy indicator is notwithin the ±1/X₁ Hz threshold, then the frequency of clock 112 hastransitioned outside the initial tolerance limits and phase 1 isrestarted at control block 202. If, at decision block 214, the accuracyindicator is within the ±1/X₁ Hz threshold, then a check is made atdecision block 216 to determine if X₁ second(s) has expired since thelast incremental frequency measurement was made. Decision block 216loops back onto itself until X₁ second(s) has expired. It should benoted that if the measured frequency at control block 208 is the firstsample, then there are no previous frequency samples so normalization isnot performed. It is assumed the first partial measurement is within ±1Hz of the actual frequency clock 112. In this case, control blocks 212to 214 are bypassed.

Upon expiration of the X₁-second timer, an examination of the fullfrequency measurement timer (e.g. the 128-second timer) transpires atdecision block 218. If the 128-second timer has not expired, incrementalfrequency measurements are continuously taken at every X₁ second(s) inaccordance with blocks 208 to 216 for the remainder of the 128-secondperiod. As stated, the accuracy of the incremental frequencymeasurements in the full 128-second period increases with eachsubsequent measurement, eventually converging upon the frequencymeasurement to within the full accuracy frequency measurement of ± 1/128Hz.

If the 128-second timer has expired at decision block 218, then Phase 1rolls over to Phase 2, which begins by storing the converged-uponmeasured frequency in a memory of node 102 at control block 220.

Phase 2 at transmitting node 102 accounts for any transitions or driftsin the frequency of user clock 112 once full accuracy is achieved inphase 1. At control block 221, a Phase 2 indicator is set that will betransmitted to receiving node 104 to trigger Phase 2 therein. At controlblock 222, the frequency measurement hardware of node 102 takes afrequency measurement of the clock signal frequency. After an X₂-secondinterval at control block 224, a frequency measurement is retrieved fromthe frequency measurement counter at control block 226. This frequencymeasurement is tagged with the Phase 2 indicator for transmission toreceiving node 104 across network 106 at control block 225. At decisionblock 228, the frequency measurement is compared to the stored, fullaccuracy frequency measurement. If the frequency measurement is within a±1/X₂ Hz limit of the stored frequency measurement, it is determinedthat no gross transition or drift has occurred, and Phase 2 continues tomonitor user clock 112 by looping back to control block 222. If thefrequency measurement is not within the limit, it may be concluded thatuser clock 112 has drifted outside the ±1/X₂ Hz tolerance limitindicating a gross transition or drift. To recapture the new frequency,Phase 1 is re-initiated at control block 230, wherein an X₃-secondinterval elapses to allow the frequency drift to settle beforeattempting to recapture the frequency in Phase 1.

It should be appreciated that the intervals of X1, X2, X3 may beidentical or differing time durations, and may be designated by any unitof time.

During Phase 1 and Phase 2, transmitting node 102 packages serial datafrom DTE 110 into digital packets that are transmitted to receiving node104.

FIG. 3 is a graph showing the changing accuracy indicators of frequencymeasurements as a function of time. In this example, clock measurementsare made at 1-second intervals for the 128-second period. Starting witha clock frequency measurement within 1 Hz of the actual clock frequency,the frequency measurements quickly converge on the actual frequency—at1-second, the accuracy indicator is within ±1 Hz; at 2-seconds, theaccuracy indicator is within ±½ Hz; at 3-seconds, the accuracy indicatoris within ±⅓ Hz; etc. At the termination of the 128-second period, thefrequency measurement is to full accuracy within ± 1/128 Hz. The fullaccuracy frequency measurement is transmitted across network 106 totransmitting node 104.

Using an example, accuracy to within ± 1/128 Hz at 1.024 MHz correspondsto 8 ppb (parts per billion). Comparing this accuracy to that of knownstandards, 1.024 MHz clocks running at Stratum 3 accuracy translates to7 Hz or 7 ppm (parts per million). In this example, the presentinvention improves accuracy in clock frequency by three orders ofmagnitude.

FIG. 4 shows control flow of a recovery process 400 performed atreceiving node 104. The demarcation between Phase 1 steps and Phase 2steps is shown. Phase 1 begins at control block 402, when receiving node104 pulls a digital packet containing a frequency measurement and aphase indicator from network 106. At decision block 404, node 104 checksfor a Phase 1 indicator and if one is found, the synthesizing hardwareat control block 406 is set to generate a comparable frequency. In thismanner, the frequency of clock 112 is recovered to the latestincremental measurement of increasing accuracy. In accordance with theplurality of incremental frequency measurements of Phase 1 taken duringthe 128-second period at node 102, control block 406 will continuelooping back to control block 402, thereby accounting for each of theincremental frequency measurements to the full accuracy within ± 1/128Hz.

The generating hardware preferably has sufficient granularity in itsfrequency output to generate a clock signal to within ± 1/128 Hzaccuracy. A DDS is capable of generating frequencies with thisgranularity may be used. While a DDS is not required, it is importantthat the clock generator be able to synthesize frequencies withsufficient granularity to take advantage of the increasingly accuratemeasurements.

If a frequency measurement tagged with a Phase 2 indicator is receivedat receiving node 104 at decision block 404, serial data packaged intodigital packets accumulate in a buffer maintained by receiving node 104.

In addition, as will be apparent to one skilled in the art, buffer fillmeasurements may begin accumulating sometime before Phase 2 actuallystarts. For example, packets may begin accumulating in the buffer duringPhase 1. These measurements may or may not be used until Phase 2.

As buffer fill measurements begin to accumulate at block 408, process400 shifts from Phase 1 to Phase 2 at receiving node 104. The bufferanalysis may indicate the presence of free-running clock signals atnodes 102, 104, as will be discussed herein. In Phase 2, standard packetarrival monitoring mechanisms are used to “fine-tune” the frequency tomaintain an average buffer fill to prevent errors on the circuit. Sincethe network infrastructure is packet-based, many different components ofjitter will be introduced on the circuit data due to congestion,queuing, time of day, etc. These must be averaged and filtered out overlong periods of time. Since recovered end clock circuit is within 1/128HZ of the correct frequency, in Phase 2, data can be gathered andanalyzed to determine if buffer fill trends indicate adjustments to therecovered frequency are needed.

At control block 410, node 104 pulls a digital packet containing afrequency measurement and phase indicator from network 106. At decisionblock 412, node 104 checks for a Phase 1 indicator, and if one is found,Phase 1 restarts by setting the current operating frequency at controlblock 406 in accordance with the frequency measurement of the mostrecently received digital packet. Alternatively, if a Phase 2 indicatoris contained in the packet, then Phase 2 continues at decision block414.

FIG. 4 illustrates one embodiment of processing Phase 2 at the receivingnode that uses buffer average monitoring. Alternative embodiments arediscussed below.

In the embodiment shown in FIG. 4, the mechanism for adaptive clockingin an IP network is to monitor the level of the buffer that receivesdata from the network. In a simple feedback control mechanism, the clockwould adjust to pull data from the Rx buffer to maintain a constantbuffer level. If the rate at which data arrives from the networkincreases, the buffer will begin to fill up. To compensate, the clockpulling data from the buffer must be increased to bring the buffer levelback to normal. Similarly, if the data rate from the network decreases,the buffer will start to deplete, and the clock must be decreased.

At decision block 414 of FIG. 4, a user-specified buffer monitor timeris checked for expiration. The timer duration designates the time windowfor accumulating buffer samples in the buffer before trend analysis isperformed. If the buffer timer has not yet expired, then there may notbe enough data in the buffer to perform trend analysis. Remote port 114may continue receiving the most recent frequency measurements at controlblock 410 as the buffer continues to accumulate more data.Alternatively, if the buffer monitoring timer has expired, theaccumulated buffer samples undergo processing at control blocks 416 to426.

At control block 416, an analysis is performed on the accumulated buffersamples to determine the components of variation in data packet arrivaltime to port 120 through network 106. Among the components of variationare frequency, magnitude, standard deviation, and averaging. A varietyof techniques may be used to find these components, including the FastFourier Transform (FFT), which is a simple numerical method fordetermining the frequency components present in sampled digital data.

Upon completion of the sampled data analysis, the average buffer depthand buffer trends are calculated at control blocks 418 and 420,respectively, using a buffer monitoring and analysis tool. Preferably,the buffer tool has short-term and long-term monitoring and analysiscapabilities for the reasons described below.

It should be appreciated that as stated earlier, node clocks 109, 111 onnodes 102 and 104 respectively, are preferably referenced to an accurateclock source 115 so that their frequencies are synchronized. Thissupports Phase 1 of the adaptive clocking process, so that the measuredfrequency value at local port 108 is the same as the recovered frequencyat remote port 114, and the only difference between user clock 112 andthe recovered frequency is the accuracy of the clock measurement.However, when node clocks 109, 111 are not referenced to the same clocksource, they are considered to be “free-running”. In this case, therecovered frequency will differ from user clock 112 not only by theaccuracy of the measurement, but also by the magnitude of the differencein node clocks 109, 111.

This frequency difference between node clocks 109, 111 may be as much as100 ppm (parts per million). If we take the example of a 1.024 MHzcircuit, this is a frequency difference of 100 Hz. So, at the end ofPhase 1 on frequency locked nodes, the recovered frequency is within1/128 Hz of user clock 112. However, if these same node clocks 109, 111are free-running and differ by 100 ppm, the recovered frequency atremote port 114 will differ by 100 Hz. This means that the Phase 2portion of the process should be capable of discerning this frequencydifference quickly in order to adapt before buffer over or under flowoccurs. This may be achieved by the Phase 2 buffer monitoring processhaving short- and long-term average results. If the short term resultindicates that the buffer level is not changing rapidly, it may beassumed that the node clocks are locked and the long term buffermonitoring performed during Phase 2 is sufficient to converge on anacceptable recovered user clock. If, however, the short term resultsindicate that the buffer level is changing quickly, the average bufferfill rate will be calculated so that the recovered clock synthesizerrate can be adjusted to maintain a constant buffer fill. Over time, theproper recovered frequency may then be realized. Once the frequencydifference between the nodes has been determined, the background grossfrequency monitoring process (Phase 1) should be adjusted to compensatefor the difference.

This is shown in steps 416-424 of FIG. 4. If, upon analysis, theshort-term results indicate that the buffer depth is not changingrapidly, it will be assumed that node clocks 109, 111 are synchronizedand that the long-term buffer monitoring process will suffice toconverge on an acceptable clock.

If at control block 422 the short-term results indicate that the averagebuffer depth is changing too quickly, the buffer tool will calculate theaverage buffer fill rate and adjust the recovery clock generator atcontrol block 424 in order to maintain a constant buffer fill. Thebuffer monitor timer is then reset at control block 426, which thenloops control back to control block 414 for continuous monitoring untila Phase 1 transition event is encountered at decision block 412.

In another embodiment of the present invention, an improved method ofadaptive clocking that filters the variable packet delay from thereceived data to extract the transmitting clock frequency.

FIG. 5 illustrates a possible behavior scenario for an IP network. FIG.5 shows many variations in packet delay for the data being transmittedthrough an IP network. For an initial time period (A), the packet delayvariation is relatively small. However, at a later time, the packetdelay variation increases (B). If the above method of buffer averagingis used, the result might be something like line 501. If the variationin this average value is many milliseconds, the resulting clockvariations will be unacceptable.

FIG. 6 illustrates variations in the transmitting clock and packet delayof the IP network. The points in the graph represent the variability indelay that a packet may experience when it travels through an IPnetwork. As shown, some packets take longer than others. Those packetsthat take longer are usually delayed by being queued behind otherpackets in the IP routers. There are some packets, however, which are“lucky”, and manage to traverse the network with a minimum of delay. Itis reasonable to assume that there are a percentage of these packetsthat will occur statistically during a given period of time. If theseare the only packets that are used to determine the trends in bufferfill (and subsequently clocking), a much more accurate evaluation can bemade.

As shown in FIG. 6, line 601 represents the clock inserting data intothe network, while the curve 602 is the network delay. By averaging allof the data in the graph, both elements are incorporated, as shown inFIG. 5. But if only the “lucky packet” line 601 is used, the packetdelay variation is effectively filtered out, leaving the transmittingclock synchronizing information. Essentially, if there is no delay dueto the IP network, the arrival rate of the “lucky” packets mimics thetransmitting clock signal.

The method of this embodiment separates the clock variation from the IPnetwork packet delay variation and filters out the packet delayvariation. The extracted clocking information is used to derive a clockto maintain buffer fill.

The data used are measurements that represent the current buffer fillvalue. These are actually timer measurements. A timer is started when apacket arrives from the network and is placed in the Rx buffer. Thetimer is stopped when that same packet is pulled from the buffer to besent to the receiving DTE. The time value is then stored. When a newpacket arrives from the network, another timer measurement starts. Thisprocess continues indefinitely.

To find a “lucky packet”, in one embodiment a fixed number ofmeasurements are grouped, and then the “luckiest” three packets arelocated in this group. Obviously, fewer or more than three packets couldbe used.

These three measurements represent the points on which the lucky packetline will “rest” in a graph. A slope is calculated from these points torepresent the line. FIG. 7 illustrates this concept.

As shown in FIG. 7, during a first period of time, points 710, 711 and712 are determined to the be the luckiest packets. These are the packetsthat stayed in the buffer the longest amount of time during the firstperiod. The slope of line 701 is calculated from points 710, 711 and712. However, in the second period, the three luckiest packets 720, 721,and 722 occurred within a short period of time. Therefore, calculatedline 702 is representative of the trend in that period, and is not agood approximation of the transmitting clock.

As shown in FIG. 8, in a preferred embodiment, a “lever” is applied tothe line by incorporating the “luckiest” packet in the previous timeperiod, 710. By using packet 710 as a “handle”, the line 802 shows amore accurate trend analysis of the data.

The slope represents the direction and magnitude of the clock differencebetween the transmitting and receiving nodes of the network. If theslope of the line is positive, the buffer values are increasing, whichmeans that data is staying in the buffer progressively longer. If thedata is in the buffer longer, the clock pulling data from the buffer istoo slow and needs to be sped up. The slope represents the magnitude ofthe needed clock adjustment. Likewise, if the slope is negative, theclock is too fast. When the slope is zero, the clocks are synchronous.

One embodiment of the adaptive clocking method of the present inventionis a multistage process that uses the slope calculations to makeadjustments. In a preferred embodiment, four stages may be used. FIG. 9illustrates the first three stages.

The first stage may be termed “Aggressive.” The purpose of this stage isto quickly make a slope determination and clock adjustment to try toavert an imminent buffer over or underflow. It is possible that theclocks are significantly off frequency from one another at each end ofthe network. For example, the clock may be 100 ppm out of sync. Withthis magnitude of difference, the Rx buffer is in imminent danger ofunder or overflow. Therefore, relatively rapid coarse adjustments mustbe made to the clock to at least slow down the rate at which the bufferis moving towards empty or full. During each of the sample groups (A-E)a slope is calculated and a clock adjustment made. The adjustment to theclock is intended to result in a slope calculation of 0 in the nextperiod. The example shown in FIG. 7 illustrates overcompensation in theclock adjustment, since the slope is alternating from positive tonegative slope. Success is achieved in this first stage when thecalculated slope falls below a specified threshold. In the example shownin FIG. 7, this occurs during period E. The process then moves to the“Aggressive/Maintain” stage.

When the process moves to the “Aggressive/Maintain” stage, the currentbuffer fill value (extrapolated from the luckiest packet of the mostrecent group with the calculated slope) is saved and recorded as the“goal” buffer fill. From this point forward, all clock adjustments willbe made in an attempt to drive the fill of the buffer to this recordedvalue. Every group will therefore now include a buffer error, which isthe difference between the current buffer fill and the “goal” bufferfill, as well as a slope calculation. In the “Aggressive/Maintain”stage, attempts to drive the error to 0 in a minimum amount of time aremade. The slope value at the beginning of the “Aggressive/Maintain”stage depend on the threshold value set for transition from the previousstage. If the threshold is very small, the clock is already close to theproper frequency and the “Aggressive/Maintain” stage may be quite short.However, setting the threshold to a very small value may cause theadaptive clock state machine to stay in the “Aggressive” state for avery long period of time if the IP network delay variation is high.Therefore, the threshold slope is preferably set to a larger value, inorder to exit the “Aggressive” stage as soon as possible.

During periods F through J, slope and error calculations and clockadjustments are made in an attempt to reduce the error to 0. The slopeis used to adjust the clock to the correct frequency, while the errorvalue is used to make a clock adjustment to reduce the error value. Acombination of these two values yields a clock adjustment that shouldeventually converge on the recorded buffer fill set point.

In the “Aggressive” stage, there is no limitation on the clockadjustment. In the “Aggressive/Maintain” stage, there is preferably aconfigurable cap on the adjustments that can be made on the clock pergroup period. This cap may have the effect of dampening clockadjustments. However, when near the target frequency and buffer level,smaller adjustments to the clock are better than large ones since therewill be a tendency to “smooth the bumps” in frequency adjustments.

It is desirable to exit the “Aggressive” stage as soon as possible asradical clock adjustments can be made during this stage, which may haveadverse effects on user equipment.

When the transition is made between “Aggressive” and“Aggressive/Maintain” states, another threshold value is preferably set.This threshold determines when to go back to the “Aggressive” state whenthe buffer error value has gotten too large. If the“Aggressive/Maintain” state is entered with a relatively small slope,the clock frequency is close to correct and not many adjustments will beneeded to bring the slope to 0. However, tif the slope is larger as itenters the “Aggressive/Maintain” state, more work will be needed tobring the slope to 0.

FIG. 9 illustrates this concept. Lines 901 and 902 represent potentialthresholds for the maximum buffer error. If line 902 is used, at groupG, the state would be set back to Aggressive. However, if 901 is used,the process will remain in the “Aggressive/Maintain” state until theerror is brought to 0 by the end of group J. It is preferably toconfigure the parameters for adaptive clocking such that transitionsfrom “Aggressive/Maintain” back to “Aggressive” are rare.

In the “Aggressive/Maintain” state, the process will find and record thetime at which the slope becomes zero. When the slope is zero, the clockis at the correct frequency. However, it is also desirable to achievezero buffer error. In the “Aggressive/Maintain” state, it is not likelythat the buffer error is zero when the slope is zero. This situation isshown in Group H of FIG. 9. If the clock value at group H is recorded asa zero slope value, then used at group J, it is possible to quicklyconverge on both zero slope and zero buffer error.

After the buffer error is driven to zero in the “Aggressive/Maintain”stage, the process moves to the “Maintain” stage. Although the buffererror is zero, there may still be a non-zero slope. If this is the case,the buffer error will increase in the opposite direction and will needto be corrected in the “Maintain” stage. As shown in FIG. 9, the processwill continue to oscillate the buffer fill around the zero error point,line 901. The zero error point is the correct buffer fill. Eventually,it will settle to the desired state of zero buffer error and zero slope.

With the use of a zero-slope clock value, large oscillations areeliminated completely. When the zero-slope clock value is used at thetime when the buffer error is zero, no more convergence is needed. Themechanism driving the buffer error to zero is the same in both the“Aggressive/Maintain” stage and the “Maintain” stage. However, duringthe “Aggressive/Maintain” stage, larger clock adjustments are allowed tobring the slope to zero as quickly as possible. When the process movesto the “Maintain” stage, the slope and the buffer error are both zero, amuch smaller clock adjustments can be used to gain the benefits ofsmoothing. Although the slope is still calculated and used to derive aclock adjustment value, it is expected to be close to zero and not playa significant role.

As shown in FIGS. 9 and 10, the clock and buffer error will oscillatearound the set buffer level indefinitely. If the group sizes are chosenappropriately, there will be enough “lucky packets” in each group to geta good buffer fill estimation independent of the IP network latency.

In the “Maintain” stage the buffer error will have a tendency tooscillate around the set buffer point, which correlates to oscillationof the clock around the “correct” frequency. If long-term averagingtechniques are used to follow these oscillations over very long periodsof time, a very accurate representation of the remote clock may bederived. This value, once found, may be stored in nonvolatile memory tobe used as the starting point should an anomaly occur which wouldnormally require a transition back to the “Aggressive” stage. Instead,the saved derived value can set the clock straight into the “Maintain”stage, assuming that the initial clock value is very close to correct.

As shown in FIG. 10, the fourth stage, the “Derived” stage, makes evensmaller clock adjustments. This has a greater clock smoothing effect,and reduces the oscillations around the buffer set point.

It should be appreciated that this system architecture does not need tobe configured to operate at a specific rate. This architecture iscapable of pass-through timing on a circuit to any rate within thesynthesis range of the clock recovery circuit, without the need toreconfigure the rate. When the frequency measurement circuit starts, itwill measure the frequency of network bound user data, no matter whatthe frequency is. The accuracy result of 1/(measurement period) Hz isalso independent of port rate. It should be appreciated that the128-second measurement period may be adjusted to fit the needs of thesystem.

While this invention has been described in conjunction with specificembodiments thereof, the preferred embodiments of the invention as setforth herein, are intended to be illustrative, not limiting.

1. A system for transmitting a clock signal through a packet-based network comprising: a first node configured to measure a clock frequency of the clock signal and calculate an accuracy indicator of the measured clock frequency; a second node configured to receive the clock frequency measurement and the accuracy indicator of the clock frequency measurement, and synthesize the clock signal therefrom; and a packet-based network for transmitting the measured clock frequency and accuracy indicator from the first node to the second node.
 2. A system for transmitting bit synchronous data through a packet-based network comprising: a first node configured to receive the bit synchronous data for transmission through the network, the first node including measurement hardware for generating a clock frequency measurement of the bit synchronous data and an accuracy indicator, the clock frequency measurement and the accuracy indicator to be transmitted through the network; and, a second node configured to receive the clock frequency measurement and accuracy indicator from the network, the second node including signal synthesizer hardware for synthesizing a clock signal from the clock frequency measurement and accuracy indicator for retrieving the bit synchronous data; wherein the measurement hardware measures a number of counts during a predetermined period of time and the accuracy indicator is a period of time for measuring the number of counts.
 3. A method for adaptive clocking in a packet-based network between a first node and a second node, comprising the steps of: receiving a clock signal for transmission through the network at the first node; measuring the clock signal to obtain a frequency measurement at the first node; determining an accuracy indicator for the measured frequency measurement at the first node; transmitting the frequency measurement and the accuracy indicator through the network from the first node to the second node; receiving the frequency measurement and the accuracy indicator at the second node; deriving a clock signal from the frequency measurement and the accuracy indicator at the second node; and transmitting the derived signal from the second node to a user equipment connected to the second node.
 4. In a packet-based network with a first transmitting node and a second receiving node, a method of determining a frequency of a transmitting clock at the second receiving node, said method comprising the steps of: receiving a first plurality of packets; determining a total time for transmission for each packet; identifying a predetermined number of packets in the plurality of received packets that have the shortest total transmission times; deriving the frequency of the transmitting clock by use of the identified predetermined number of packets.
 5. The method of claim 4, wherein the derived frequency is used maintain buffer fill at the second receiving node.
 6. The method of claim 4, additionally comprising the steps of: identifying the packet in the first plurality of received packets that has the shortest total transmission time; receiving a second plurality of packets; determining a total time for transmission for each packet in the second plurality of packets; identifying a predetermined number of packets in the second plurality of received packets that have the shortest total transmission times; deriving the frequency of the transmitting clock through the identified predetermined number of packets in the second plurality of packets and the identified packet with the shortest total transmission time in the first plurality of packets. 